1:10 clock fanout buffe r cy2cc810 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-07056 rev. *e revised september 5, 2006 features ? low-voltage operation ?v dd range from 2.5v to 3.3v ? 1:10 fanout ? over voltage tolerant input hot swappable ? drives either a 50-ohm or 75-ohm transmission line ? low-input capacitance ? 250 ps typical output-to-output skew ? 19 ps typical dj jitter ? typical propagation delay < 3.5 ns ? high-speed operation > 500 mhz ? industrial versions available ? available packages in clude: soic, ssop description the cypress series of network circuits are produced using advanced 0.35-micron cmos technology, achieving the industry?s fastest logic and buffers. the cypress cy2cc810 fanout buffer features one input and ten outputs. designed for data communications clock management applications, the la rge fanout from a single input reduces loading on the input clock. avcmos-type outputs dynamically adjust for variable impedance matching and reduce noise overall. . block diagram pin configuration output (avcmos) in q1 q5 q7 q6 q4 q3 q2 q8 q9 q10 gnd vdd input 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 cy2cc810 20 pin soic/ssop vdd q10 q9 gnd q8 vdd q7 gnd q6 q5 in gnd q1 vdd q2 gnd q3 vdd q4 gnd pin description pin number pin name description 1 in input lvcmos 2, 6, 10, 13, 17 gnd ground power 4, 8, 15, 20 v dd power supply power 3, 5, 7, 9, 11, 12, 14, 16 , 18, 19 q1... q10 output avcmos [+] feedback
cy2cc810 document #: 38-07056 rev. *e page 2 of 9 absolute maximum conditions [1, 2] parameter description min. max. unit v dd v dd ground supply voltage ?0.5 4.6 v v in input supply voltage to ground potential ?0.5 5.8 v v out output supply voltage to ground potential ?0.5 v dd +1 v t s temperature, storage ?65 150 c t a temperature, operating ambient ?40 85 c power dissipation 0.75 w dc electrical characteristics @ 3.3v (see figure 5 ) parameter description cond itions min. typ. max. unit v oh output high voltage v dd = min., v in = v ih or v il i oh = ?12 ma 2.3 3.3 v v ol output low voltage v dd = min., v in = v ih or v il i ol = 12 ma 0.2 0.5 v v ih input high voltage guaranteed logic high level 2 5.8 v v il input low voltage guaranteed logic low level 0.8 v i ih input high current v dd = max. v in = 2.7v 1 a i il input low current v dd = max. v in = 0.5v ?1 a i i input high current v dd = max., v in = v dd (max.) 20 a v ik clamp diode voltage v dd = min., i in = ?18 ma ?0.7 ?1.2 v i ok continuous clamp current v dd = max., v out = gnd ?50 ma o off power down disable v dd = gnd, v out = < 4.5v 100 a v h input hysteresis v dd = min., v in = v ih or v il 80 mv dc electrical characteristics @ 2.5v (see figure 1 ) parameter description cond itions min. typ. max. unit v oh output high voltage v dd = min., v in = v ih or v il i oh = ?7 ma 1.8 v i oh = 12 ma 1.6 v v ol output low voltage v dd = min., v in = v ih or v il i ol = 12 ma 0.65 v v ih input high voltage guaranteed logic high level 1.6 5.0 v v il input low voltage guaranteed logic low level 0.8 v i ih input high current v dd = max. v in = 2.4v 1 a i il input low current v dd = max. v in = 0.5v ?1 a i i input high current v dd = max., v in = v dd (max.) 20 a v ik clamp diode voltage v dd = min., i in = ?18 ma ?0.7 ?1.2 v i ok continuous cla mp current v dd = max., v out = gnd ?50 ma o off power-down disable v dd = gnd, v out = < 4.5v 100 a v h input hysteresis 80 mv note 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is intended to be a stress rating only and functional operation of the device at these or any other condi tions above those indicated in the operation sections of this spe cification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. multiple supplies: the voltage on any input or i/o pin cannot exceed the power pin during power-up. power supply sequencing i s not required. capacitance parameter description test conditions min. typ. max. unit cin input capacitance v in = 0v 2.5 pf cout output capacitance v out = 0v 6.5 pf [+] feedback
cy2cc810 document #: 38-07056 rev. *e page 3 of 9 power supply characteristics (see figure 5 ) parameter description test conditions min. typ. max. unit ? icc delta i cc quiescent power supply current (i dd @ v dd = max. and v in = v dd ) ? (i dd @ v dd = max. and v in = v dd ? 0.6v) 50 a i ccd dynamic power supply current v dd = max. input toggling 50% duty cycle, outputs open 0.63 ma/ mhz i c total power supply current v dd = max. input toggling 50% duty cycle, outputs open fl = 40 mhz 25 ma t pu power-up time for all v dd s power-up to reach minimum specified voltage (power ramp must be monotonic) 0.05 500 ms high-frequency parametrics parameter description test conditions min. typ. max. unit d j jitter, deterministic 50% duty cycle t w (50?50) the ?point to point load circuit? output jitter ? input jitter 2.5v 23 35 ps 3.3v 19 30 ps f max(3.3v) maximum frequency v dd = 3.3v 50% duty cycle t w (50?50) standard load circuit. see figure 5 160 mhz 50% duty cycle t w (50?50) the ?point to point load circuit? see figure 7 650 f max(2.5v maximum frequency v dd = 2.5 v the ?point to point load circuit? v in = 2.4v/0.0v v out = 1.7v/0.7v see figure 7 200 mhz f max(20) maximum frequency v dd = 3.3 v 20% duty cycle t w (20?80) the ?point to point load circuit? v in = 3.0v/0.0v v out = 2.3v/0.4v see figure 7 250 mhz maximum frequency v dd = 2.5 v the ?point to point load circuit? v in = 2.4v/0.0v v out = 1.7v/0.7v see figure 3 200 mhz t w minimum pulse v dd = 3.3 v the ?point to point load circuit? v in = 3.0v/0.0v f = 100 mhz v out = 2.0v/0.8v see figure 7 1ns minimum pulse v dd = 2.5 v the ?point to point load circuit? v in = 2.4v/0.0v f = 100 mhz v out = 1.7v/0.7v see figure 3 1 ac switching characteristics @ 3.3v, v dd = 3.3v 5%, temperature = ?40 c to +85 c parameter description min. typ. max. unit t plh propagation delay ? low to high see figure 4 1.5 2.7 3.5 ns t phl propagation delay ? high to low 1.5 2.7 3.5 ns t r output rise time 0.8 v/ns t f output fall time 0.8 v/ns t sk(0) output skew: skew between outputs of the same package (in phase) see figure 10 0.25 0.38 ns t sk(p) pulse skew: skew between opposite transitions of the same output (t phl ? t plh ). see figure 9 0.2 ns t sk(t) package skew: skew between outputs of different packages at the same power supply voltage, temperature and package type. see figure 11 0.42 ns [+] feedback
cy2cc810 document #: 38-07056 rev. *e page 4 of 9 parameter measurement information: v dd @2.5v figure 1. load circuit [3,4,5] f figure 2. voltage waveforms pulse duration [6] figure 3. point to point load circuit [3,4,5] ac switching characteristics @ 2.5v, v dd = 2.5v 5%, temperature = ?40 c to +85 c parameter description min. typ. max. unit t plh propagation delay ? low to high see figure 4 1.5 2.0 3.5 ns t phl propagation delay ? high to low 1.5 2.0 3.5 ns t r output rise time 0.8 v/ns t f output fall time 0.8 v/ns t sk(0) output skew: skew between outputs of the same package (in phase) see figure 10 0.25 0.38 ns t sk(p) pulse skew: skew between opposite transitions of the same output (t phl ? t plh ). see figure 9 0.4 ns t sk(t) package skew: skew between outputs of different packages at the same power supply voltage, temperature and package type. see figure 11 0.65 ns notes 3. c l includes probe and jig capacitance. 4. all input pulses are supplied by generators having the following characteristics: prr < 100 mhz, z 0 = 50w, t r < 2.5 ns, t f < 2.5 ns. 5. the outputs are measured one at a time with one transition per measurement. 6. t plh and t phl are the same as t pd .. f ro m o u tp u t under test c l = 50 pf 500 ohm 2.0 v 0 v input t w(20-80) 2.0 v 0 v 1.25 v 1.25 v input t w(50-50) 1.25 v from output under test c l = 3 pf 500 ohm [+] feedback
cy2cc810 document #: 38-07056 rev. *e page 5 of 9 figure 4. voltage waveformspropagation delay times [4] parameter measurement information: v dd @3.3v figure 5. load circuit [3,4,5] figure 6. voltage waveforms?pulse duration [6] figure 7. point to point load circuit [3,4,5] figure 8. voltage waveforms propagation delay times [4] 1.25 v 1.25 v 1.25 v 1.25 v t plh t phl 2.0 v v oh v ol 0 v input output from output under test c l = 50 pf 500 ohm 2.7v 0 v input t w(20-80) 2.7v 0 v 1.5v 1.5v input t w(50-50) 1.5v from output under test c l = 3 pf 500 ohm 1.5v 1.5v 1.5v 1.5v t plh t phl 2.7v v oh v ol 0 v input output [+] feedback
cy2cc810 document #: 38-07056 rev. *e page 6 of 9 figure 9. pulse skew?tsk (p) figure 10. output skew?tsk (0) figure 11. package skew?tsk (t) input output t plh t phl tsk (p) = l t phl - t plh l 3v 1.5v 0v voh 1.5v vol in p u t output 1 t plh1 t phl1 tsk (p) = l t plh2 - t plh1 l or t phl2 - t phl1 l 3v 1.5v 0v voh 1.5v vol output 2 voh 1.5v vol tsk (o ) tsk (o ) t plh 2 t plh 2 input package 1 output t plh1 t phl1 tsk (t) = l t plh2 - t plh1 l or t phl2 - t phl1 l 3v 1.5v 0v voh 1.5v vol package 2 output voh 1.5v vol tsk (t) tsk (t) t plh 2 t plh 2 [+] feedback
cy2cc810 document #: 38-07056 rev. *e page 7 of 9 package drawing and dimensions figure 12. 20-lead (300-mil) soic s20.3/sz20.3 ordering information part number package type product flow cy2cc810oi 20-pin ssop industrial, ?40 c to 85 c cy2cc810oit 20-pin ssop?tape and reel industrial, ?40 c to 85 c cy2cc810oc 20-pin ssop commercial, 0 c to 70 c cy2cc810oct 20-pin ssop?tape and reel commercial, 0 c to 70 c lead-free cy2cc810oxc 20-pin ssop commercial, 0 c to 70 c cy2cc810oxct 20-pin ssop?tape and reel commercial, 0 c to 70 c cy2cc810oxi 20-pin ssop industrial, ?40 c to 85 c cy2cc810oxit 20-pin ssop?tape and reel industrial, ?40 c to 85 c pin 1 id seating plane 0.497[12.623] 0.513[13.030] 1 10 11 20 * * * 0.291[7.391] 0.300[7.620] 0.394[10.007] 0.419[10.642] 0.050[1.270] typ. 0.092[2.336] 0.105[2.667] 0.004[0.101] 0.0118[0.299] 0.0091[0.231] 0.0125[0.317] 0.015[0.381] 0.050[1.270] 0.013[0.330] 0.019[0.482] 0.026[0.660] 0.032[0.812] 0.004[0.101] part # s20.3 standard pkg. sz20.3 lead free pkg. min. max. note : 1. jedec std ref mo-119 2. body length dimension does not include mold protrusion/end flash,but mold protrusion/end flash shall not exceed 0.010 in (0.254 mm) per side 3. dimensions in inches 4. package weight 0.55gms does include mold mismatch and are measured at the mold parting line. 51-85024-*c [+] feedback
cy2cc810 document #: 38-07056 rev. *e page 8 of 9 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems wh ere a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. figure 13. 20-lead (5.3-mm) shrunk small outline package o20 all product and company names mentio ned in this document are the tradema rks of their respective holders. 51-85077-*c [+] feedback
cy2cc810 document #: 38-07056 rev. *e page 9 of 9 document history page document title: cy2cc810 1:10 clock fanout buffer document #: 38-07056 rev. ecn no. issue date orig. of change description of change ** 107081 06/07/01 ika convert from imi to cypress *a 114315 05/09/02 tsm ? i dd validation *b 119117 10/07/02 rgl added 5.8 as the max. value of v ih in the dc electrical characteristics @3.3v table. changed the max. value of v ih from 1.8 to 5.0 in th e dc electrical charac- teristics @2.5v table. *c 122743 12/14/02 rbi added power up requirements to maximum ratings information. *d 387761 see ecn rgl added typical values updated jitter and skew specs. removed devices with soic package added lead-free ssop package *e 499991 see ecn rgl added tpu parameter in the power supply characteristics table [+] feedback
|
